Recent advances in Field Programmable Gate Array (FPGA) architectures have led to both reduced size of routing multiplexer (or mux) due to NMOS/CMOS scaling as well as track number reduction in the horizontal direction caused by shrinks in wire size and a need to keep layer counts reasonable. These changes have reduced the connectivity between general routing of interconnect wires and configurable logic block (CLB) input pins. Current approaches to deal with the connectivity issue utilize interconnect node or inode structures used to add connectivity to a single slice of CLB. Here, the inode structures are nodes for interconnect that can also be the interface to the general routing.
As the size of transistors in the CLB continues to scale down, the interconnect wires do not scale down accordingly, resulting in less area available for general routing of the interconnect wires. In the meantime, the CLB size of some FPGA architectures has increased by multiple folds. Consequently, using a lot of interconnect wires across the slices of the CLB is becoming less viable.